CT-2001A



Robot Cerebellum Chip

CT-2001A

 

Product Brief

The CT-2001A chip adopts a superscalar ASIC architecture, achieving multi-thread concurrency with latency below 20 nanoseconds. It features an integrated FOC analog computation unit, programmable digital filtering, neural network adaptive control, and an analog IDPU "calculus processing unit," with hardware-accelerated latency as low as 0.2 ns (traditional solutions: 2.8 ns). It includes 1 MB on-chip Flash, 512 KB SRAM, 21 digital communication interfaces, and over 10 built-in hardware-accelerated cryptographic algorithms, supporting storage encryption, user partition protection, secure boot, and other security features.

Product Features

1. ASIC hardware encoding technology, 1 MB Flash, supports encrypted storage, partition management, and data protection, with ECC verification, 100,000 erase/write cycles, and 10-year data retention.

2. 512 KB SRAM with hardware parity checking.

3. Supports automatic acquisition of built-in ADC data and external SDFM data, hardware acceleration for CLARKE/PARK/PID/IPARK/SVPWM algorithms, automatic update of EPWM output duty cycle, and up to Q24 fixed-point output precision.

Technical Configuration & Specifications

Product Name

Robot Control Chip

Model

CT-2001A

Packge

BGA144

Size

10×10×1.26mm

CPU

• RISC-V 32-bit dual-core, 540 MHz

• RV32IMAFDCP instruction set

• L1 I/D-Cache 16KB/16KB

• Supports single-cycle Tightly Coupled Memory (TCM), I/D-TCM up to 128 KB + 128 KB configurable

• Hardware encoding, single/double-precision floating-point units, integrated DSP instruction set

• PMP security protection

• Core-local interrupt controller (CLINT) and CLIC

On-Chip Storage

• SRAM 512 KB (128 KB + 128 KB configurable as TCM)

• Flash 1 MB

System Boot

• Boot order configurable via eFUSE

• Supports USB/UART programming

• SiP SPI NOR supports external direct mode programming

System Security

• Digital signature secure boot

• CE for AES/TDES and SHA/HMAC algorithms

• SPI_ENC for SPI NOR online decryption

• SID built-in 512-bit eFUSE (64-bit user-defined)

• Built-in 256-bit TRNG

• JTAG lock/unlock support

System Control

Built-in THS temperature sensor, supports high/low temperature alarm and over-temperature reset

WDOG Watchdog

• Interrupt and reset, timeout configurable from 1 ms to 37 hours

• Pause or continue counting configurable in debug mode

• Hardware write protection

Clock & Power Mgmt

• Two PLLs: PLL_INT0 for CPU, PLL_FRA0 for peripherals with spread spectrum

• One built-in LDO

GPT Timer

• Four 32-bit GPTs

• Output compare signal for interrupt and pin output

Interfaces

• One USB FS device

• Up to 4 SPI (Master/Slave, QSPI)

• Up to 9 UART (16550-compatible, baud rate error <2%)

• Up to 4 I2C (7/10-bit addressing, up to 400 Kb/s)

• One CAN (CAN2.0A/B, up to 1 Mbps)

• Up to two CAN-FD (up to 10 Mbps)

Temperature

-40~125℃

FOC Hardware

• Auto acquisition of ADC/SDFM data

• Hardware acceleration for CLARKE/PARK/PID/IPARK/SVPWM

• Auto-update EPWM duty cycle

• Up to Q24 fixed-point precision

EPWM (Enhanced PWM)

• 24 channels, resolution up to 120 ps

• 16-bit counter

•  Up/down/up-down counting modes

• PWM supports internal phase synchronization

• Dead-time control

• Six fault inputs

• Support pulse group output function

SDFM (Sigma-Delta Interface)

• Supports four SDFM

• Support serial input decoding

• Support SINC 1/2/3 filters

• Support OSR configurable

ADC

• Built in two 14 bit ADCs

• The highest sampling rate is 2MSPS

• Two ADCs multiplex 16 sampling channels

• Support hardware 1/2/4/8/16/32 oversampling mode

• Support external input reference voltage

CPM (Comparator Module)

• Support external input reference voltage

• Supports up to two CPMs

• Comparison of windows with built-in 12 bit DAC reference

OPA

• Supports up to four OPAs, with programmable gain

• Support source following mode, gain amplification mode, and differential amplification mode

Typical Applications

• Servo motor driver

• BLDC motor driver


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